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1. general description the nxp semiconductors SE97 measures temperature from - 40 c to +125 c with jedec grade b 1 c accuracy between +75 c and +95 c and also provide 256 bytes of eeprom memory communicating via the i 2 c-bus/smbus. it is typically mounted on a dual in-line memory module (dimm) measuring the dram temperature in accordance with the new jedec (jc-42.4) mobile platform memory module temperature sensor component speci?cation and also replacing the serial presence detect (spd) which is used to store memory module and vendor information. the SE97 thermal sensor operates over the v dd range of 3.0 v to 3.6 v and the eeprom over the range of 3.0 v to 3.6 v write and 1.7 v to 3.6 v read. placing the temp sensor (ts) on a dimm allows accurate monitoring of the dimm module temperature to better estimate the dram case temperature (t case ) to prevent it from exceeding the maximum operating temperature of 85 c. the chip set throttles the memory traf?c based on the actual temperatures instead of the calculated worst-case temperature or the ambient temperature using a temp sensor mounted on the motherboard. there is up to 30 % improvement in thin and light notebooks that are using one or two 1 gb so-dimm modules. the ts is required on ddr3 rdimm and rdimm ecc. future uses of the ts will include more dynamic control over thermal throttling, the ability to use the alarm window to create multiple temperature zones for dynamic throttling and to save processor time by scaling the memory refresh rate. the ts consists of a ds analog-to-digital converter (adc) that monitors and updates its own temperature readings 10 times per second, converts the reading to a digital data, and latches them into the data temperature register. user-programmable registers, the speci?cation of upper/lower alarm and critical temperature trip points, event output control, and temperature shutdown, provide ?exibility for dimm temperature-sensing applications. when the temperature changes beyond the speci?ed boundary limits, the SE97 outputs an event signal using an open-drain output that can be pulled up between 0.9 v and 3.6 v. the user has the option of setting the event output signal polarity as either an active low or active high comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. the event output can even be con?gured as a critical temperature output. the eeprom is designed speci?cally for dram dimms spd. the lower 128 bytes (address 00h to 7fh) can be permanent write protected (pwp) or reversible write protected (rwp) by software. this allows dram vendor and product information to be stored and write protected. the upper 128 bytes (address 80h to ffh) are not write protected and can be used for general purpose data storage. SE97 ddr memory module temp sensor with integrated spd, 3.3 v rev. 05 6 august 2009 product data sheet
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 2 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v the SE97 has a single die for both the temp sensor and eeprom for higher reliability and supports the industry-standard 2-wire i 2 c-bus/smbus serial interface. the smbus timeout function is supported to prevent system lock-ups. manufacturer and device id registers provide the ability to con?rm the identity of the device. three address pins allow up to eight devices to be controlled on a single bus. 2. features 2.1 general features n jedec (jc-42.4) tse 2002b3 dimm 0.5 c (typ.) between 75 c and 95 c temperature sensor plus 256-byte serial eeprom for serial presence detect (spd) n optimized for voltage range: 3.0 v to 3.6 v, but spd can be read down to 1.7 v n shutdown current: 0.1 m a (typ.) and 5.0 m a (max.) n 2-wire interface: i 2 c-bus/smbus compatible, 0 hz to 400 khz n smbus alert response address and timeout (programmable) n esd protection exceeds 2500 v hbm per jesd22-a114, 250 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n available packages: tssop8, hvson8, hxson8, hwson8 (jedec pson8 vced-3) 2.2 temperature sensor features n 11-bit adc temperature-to-digital converter with 0.125 c resolution n operating current: 250 m a (typ.) and 400 m a (max.) n programmable hysteresis threshold: off, 0 c, 1.5 c, 3 c, 6 c n over/under/critical temperature event output n b grade accuracy: u 0.5 c/ 1 c (typ./max.) ? +75 c to +95 c u 1.0 c/ 2 c (typ./max.) ? +40 c to +125 c u 2.0 c/ 3 c (typ./max.) ?- 40 c to +125 c 2.3 serial eeprom features n operating current: u write ? 0.6 ma (typ.) for 3.5 ms (typ.) u read ? 100 m a (typ.) n organized as 1 block of 256 bytes [(256 8) bits] n 100,000 write/erase cycles and 10 years of data retention n permanent and reversible software write protect n software write protection for the lower 128 bytes
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 3 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 3. applications n ddr2 and ddr3 memory modules n laptops, personal computers and servers n enterprise networking n hard disk drives and other pc peripherals 4. ordering information [1] SE97tl and SE97tp offer improved v por / event i ol . [2] industry standard 2 mm 3mm 0.8 mm package to jedec vced-3 pson8 in 8 mm 4 mm pitch tape 4 k quantity reels. table 1. ordering information type number topside mark package name description version SE97pw SE97 tssop8 plastic thin shrink small outline package; 8 leads; body width 4.4 mm sot530-1 SE97tk SE97 hvson8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 3 0.85 mm sot908-1 SE97tl [1] 97l hxson8 plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 3 0.5 mm sot1052-1 SE97tp [1] [2] s97 hwson8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 3 0.8 mm sot1069-1
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 4 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 5. block diagram fig 1. block diagram of SE97 002aab349 scl sda event 2-kbit eeprom no write protect software write protect SE97 v ss smbus/i 2 c-bus interface v dd ffh 7fh 00h temperature register critical alarm trip upper alarm trip lower alarm trip capability manufacturing id device/rev id smbus timeout/alert configuration hysteresis shut down temp sensor lock protection event output on/off event output polarity event output status clear event output status pointer register band gap temperature sensor 11-bit ds adc por 10 v overvoltage filter a0 a1 a2 r 30 k w to 800 k w r 30 k w to 800 k w r 30 k w to 800 k w 80h
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 5 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for tssop8 fig 3. pin con?guration for hxson8 fig 4. pin con?guration for hvson8 fig 5. pin con?guration for hwson8 SE97pw a0 v dd a1 event a2 scl v ss sda 002aab805 1 2 3 4 6 5 8 7 terminal 1 index area 1 a0 SE97tl 002aad548 transparent top view 2 a1 3 a2 4 8 7 6 5 v ss v dd event scl sda 002aab803 SE97tk sda a2 v ss scl a1 event a0 v dd transparent top view 4 5 3 6 2 7 1 8 terminal 1 index area terminal 1 index area 1 a0 SE97tp 002aad768 transparent top view 2 a1 3 a2 4 8 7 6 5 v ss v dd event scl sda table 2. pin description symbol pin type description a0 1 i i 2 c-bus/smbus slave address bit 0 with internal pull-down. this input is overvoltage tolerant to support software write protection. a1 2 i i 2 c-bus/smbus slave address bit 1 with internal pull-down a2 3 i i 2 c-bus/smbus slave address bit 2 with internal pull-down v ss 4 ground device ground sda 5 i/o smbus/i 2 c-bus serial data input/output (open-drain). must have external pull-up resistor. scl 6 i smbus/i 2 c-bus serial clock input/output (open-drain). must have external pull-up resistor. event 7 o thermal alarm output for high/low and critical temperature limit (open-drain). must have external pull-up resistor. v dd 8 power device power supply (3.0 v to 3.6 v); supports 1.7 v for eeprom read only.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 6 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7. functional description 7.1 serial bus interface the SE97 communicates with a host controller by means of the 2-wire serial bus (i 2 c-bus/smbus) that consists of a serial clock (scl) and serial data (sda) signals. the device supports smbus, i 2 c-bus standard-mode and fast-mode. the i 2 c-bus standard speed is de?ned to have bus speeds from 0 hz to 100 khz, i 2 c-bus fast speed from 0 hz to 400 khz, and the smbus is from 10 khz to 100 khz. the host or bus master generates the scl signal, and the SE97 uses the scl signal to receive or send data on the sda line. data transfer is serial, bidirectional, and is one byte at a time with the most signi?cant bit (msb) is transferred ?rst. since scl and sda are open-drain, pull-up resistors must be installed on these pins. 7.2 slave address the SE97 uses a 4-bit ?xed and 3-bit programmable (a0, a1 and a2) 7-bit slave address that allows a total of eight devices to co-exist on the same bus. the a0, a1 and a2 pins are pulled low internally. the a0 pin is also overvoltage tolerant supporting 10 v software write protect. when it is driven higher than 7.8 v, writing a special command would put the eeprom in reversible write protect mode (see section 7.10.2 memor y protection ). each pin is sampled at the start of each i 2 c-bus/smbus access. the temperature sensors ?xed address is 0011b. the eeproms ?xed address for the normal eeprom read/write is 1010b, and for eeprom software protection command is 0110b. refer to figure 6 . a. temperature sensor b. eeprom (normal read/write) c. eeprom (software protection command) fig 6. slave address r/w 002aab304 0 0 1 1 a2 a1 a0 fixed hardware selectable slave address msb lsb x r/w 002aab351 1 0 1 0 a2 a1 a0 fixed hardware selectable slave address msb lsb x r/w 002aab352 0 1 1 0 a2 a1 a0 fixed hardware selectable slave address msb lsb x
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 7 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.3 event output condition the event output indicates conditions such as the temperature crossing a prede?ned boundary. the event modes are very con?gurable and selected using the con?guration register (config). the interrupt mode or comparator mode is selected using config[0], using either tcrit/upper/lower or tcrit only temperature bands (config[2]) as modi?ed by hysteresis (config[10:9]). the upper/lower (config[6]) and tcrit (config[7]) bands can be locked. figure 7 shows an example of the measured temperature versus time, with the corresponding behavior of the event output in each of these modes. upon device power-up, the default condition for the event output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (config[3]). event output polarity can be set to active high or active low (config[1]). event status can be read (config[4]) and cleared (config[5]). ? advisory note: C nxp device: after power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. C competitor device: does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. C work-around: in order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. C SE97b will allow bit 2 or bit 0 to be changed even if bit 3 is set. if the device enters shutdown mode (config[8]) with asserted event output, the output remains asserted during shutdown. 7.3.1 event pin output voltage levels and resistor sizing the event open-drain output is typically pulled up to a voltage level from 0.9 v to 3.6 v with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the event pin since it is simply an open-drain output. it could be pulled up to 0.1 v and would not affect the output. from the system perspective, there will be a practical limit. that limit will be the voltage necessary for the device monitoring the interrupt pin to detect a high on its input. a possible practical limit for a cmos input would be 0.4 v. another thing to consider is the value of the pull-up resistor. when a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the event pin.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 8 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v when t amb 3 t th(crit) and t amb < t th(crit) - t hys the event output is in comparator mode and bit 0 of config ( event output mode) is ignored. refer to t ab le 3 for ?gure note information. fig 7. event output condition 002aae324 time temperature ( c) critical event in interrupt mode event in comparator mode software interrupt clear lower boundary alarm upper boundary alarm event in critical temp only mode (1) (2) (1) (3) (4) (3) (5) * (6) (4) (2) t amb t trip(l) - t hys t trip(u) - t hys t th(crit) - t hys t trip(u) - t hys t trip(l) - t hys table 3. event output condition figure note event output boundary conditions event output temperature register status bits comparator mode interrupt mode critical temp only mode bit 15 above critical trip bit 14 above alarm window bit 13 below alarm window (1) t amb 3 t trip(l) hlh000 (2) t amb < t trip(l) - t hys llh001 (3) t amb > t trip(u) llh010 (4) t amb t trip(u) - t hys hlh000 (5) t amb 3 t th(crit) lll110 (6) t amb < t th(crit) - t hys lhh010
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 9 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.3.2 event thresholds 7.3.2.1 alarm window the device provides a comparison window with an upper trip point and a lower trip point, programmed through the upper boundary alarm trip register (02h), and lower boundary alarm trip register (03h). the upper boundary alarm trip register holds the upper temperature trip point, while the lower boundary alarm trip register holds the lower temperature trip point as modi?ed by hysteresis as programmed in the con?guration register. when enabled, the event output triggers whenever entering or exiting (crossing above or below) the alarm window. ? advisory note: C nxp device: the event output can be cleared through the clear event bit (cevnt) or smbus alert. C competitor device: the event output can be cleared only through the clear event bit (cevnt). C work-around: only clear event output using the clear event bit (cevnt). C there will be no change to nxp devices. the upper boundary alarm trip should always be set above the lower boundary alarm trip. ? advisory note: C nxp device: requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the alarm window and operating event output. C competitor devices: compares the alarm limit with temperature register at any time, so they get the event output immediately when new upper or lower alarm windows and the event output are set at the same time. C work-around: wait at least 125 ms before enabling event output (eoctl = 1). C SE97b will compare alarm window and temperature register immediately. 7.3.2.2 critical trip the t th(crit) temperature setting is programmed in the critical alarm trip register (04h) as modi?ed by hysteresis as programmed in the con?guration register. when the temperature reaches the critical temperature value in this register (and event is enabled), the event output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. the event cannot be cleared through the clear event bit (cevnt) or smbus alert. the critical alarm trip should always be set above the upper boundary alarm trip. ? advisory note: C nxp device: requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the alarm window and operating event output.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 10 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v C competitor devices: compares the alarm window with temperature register at any time, so they get the event output immediately when new t th(crit) and event output are set at the same time. C work-around: wait at least 125 ms before enabling event output (eoctl = 1). intel will change nehalem bios so that t th(crit) is set for more than 125 ms before event output is enabled and event value is checked. 1. set t th(crit) . 2. doing something else (make sure that exceeds 125 ms). 3. enable the event output (eoctl = 1). 4. wait 20 m s. 5. read event value. C SE97b will compare alarm window and temperature register immediately. 7.3.3 event operation modes 7.3.3.1 comparator mode in comparator mode, the event output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the upper boundary alarm trip register or below the value programmed in the lower boundary alarm trip register or above the critical alarm trip resister if t th(crit) only is selected). reads/writes on the registers do not affect the event output in comparator mode. the event signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. the comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 interrupt mode in interrupt mode, event asserts whenever the temperature crosses an alarm window threshold. after such an event occurs, writing a 1 to the clear event bit (cevnt) in the con?guration register de-asserts the event output until the next trigger condition occurs. in interrupt mode, event asserts when the temperature crosses the alarm upper boundary. if the event output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, event asserts again. because the temperature is greater than the critical temperature threshold, a clear event command does not clear the event output. once the temperature drops below the critical temperature, event de-asserts immediately. ? advisory note: C nxp device: if the event output is not cleared before the temperature goes above the critical temperature threshold event de-asserts immediately when temperature drops below the critical temperature. C competitor devices: if the event output is not cleared before or when the temperature is in the critical temperature threshold, event will remain asserted after the temperature drops below the critical temperature until a clear event command.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 11 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v C work-around: always clear the event output before temperature exceeds the critical temperature. C SE97b will keep event asserted after the temperature drops below the critical temperature until a clear event command de-asserts event. 7.4 conversion rate the conversion time is the amount of time required for the adc to complete a temperature measurement for the local temperature sensor. the conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one secondthe faster the conversion rate, the faster the temperature reading is updated. the SE97s conversion rate is at least 8 hz or 125 ms. 7.4.1 what temperature is read when conversion is in progress the SE97 has been designed to ensure a valid temperature is always available. when a read to the temperature register is initiated through the smbus, the device checks to see if the temperature conversion process (analog-to-digital conversion) is complete and a new temperature is available: ? if the temperature conversion process is complete, then the new temperature value is sent out on the smbus. ? if the temperature conversion process in not complete, then the previous temperature value is sent out on the smbus. it is possible that while smbus master is reading the temperature register, a new temperature conversion completes. however, this will not affect the data (msb or lsb) that is being shifted out. on the next read of the temperature register, the new temperature value will be shifted out. 7.5 power-up default condition after power-on, the SE97 is initialized to the following default condition: ? starts monitoring local sensor ? event register is cleared; event output is pulled high by external pull-ups ? event hysteresis is defaulted to 0 c ? command pointer is defaulted to 00h ? critical temp, alarm temperature upper and lower boundary trip register are defaulted to 0 c ? capability register is defaulted to 0017h for the b grade ? operational mode: comparator ? smbus register is defaulted to 00h 7.6 device initialization SE97 temperature sensors have programmable registers, which, upon power-up, default to zero. the open-drain event output is default to being disabled, comparator mode and active low. the alarm trigger registers default to being unprotected. the con?guration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. smbus timeout
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 12 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v feature defaults to being enabled and can be programmed to disable. these registers are required to be initialized before the device can properly function. except for the spd, which does not have any programmable registers, and does not need to be initialized. t ab le 4 shows the default values and the example value to be programmed to these registers. 7.7 smbus time-out the SE97 supports smbus time-out feature. if the host holds scl low between 25 ns and 35 ms, the SE97 would reset its internal state machine to the bus idle state to prevent the system bus hang-up. this feature is turned on by default. the smbus time-out is disabled by writing a 1 to bit 7 of register 22h. remark: when smbus time-out is enabled, the i 2 c-bus minimum bus speed is limited by the smbus time-out speci?cation limit of 10 khz. the SE97 has no scl driver, so it cannot hold the scl line low. remark: smbus time-out works over the entire supply range of 1.7 v to 3.6 v unless the shutdown bit (shmd) is set and turns off the oscillator. 7.8 smbus alert response address (ara) the SE97 supports smbus alert when it is programmed for the interrupt mode and when the event polarity bit is set to 0. the event pin can be anded with other event or interrupt signals from other slave devices to signal their intention to communicate with the host controller. when the host detects event or other interrupt signal low, it issues an ara to which a slave device would respond with its address. when there are multiple slave devices generating an alert the SE97 performs bus arbitration with the other slaves. if it wins the bus, it responds to the ara and then clears the event pin. remark: either in comparator mode or when the SE97 crosses the critical temperature, the host must also read the event status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. otherwise, the event pin will not get de-asserted. remark: in the SE97 the ara is set to default on. however, in the SE97b the ara will be set to default off since ara is not anticipated to be used in ddr3 dimm applications. table 4. registers to be initialized register default value example value description 01h 0000h 0209h con?guration register ? hysteresis = 1.5 c ? event output = interrupt mode ? event output is enabled 02h 0000h 0550h upper boundary alarm trip register = 85 c 03h 0000h 1f40h lower boundary alarm trip register = - 20 c 04h 0000h 05f0h critical alarm trip register = 95 c 22h 0000h 0000h smbus register = no change
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 13 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.9 smbus/i 2 c-bus interface the data registers in this device are selected by the pointer register. at power-up, the pointer register is set to 00h, the location for the capability register. the pointer register latches the last location to which it was set. each data register falls into one of three types of user accessibility: ? read only ? write only ? write/read same address a write to this device will always include the address byte and the pointer byte. a write to any register other than the pointer register requires two data bytes. reading this device can take place either of two ways: ? if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will point to one of the temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. ? if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. the data byte has the most signi?cant bit ?rst. at the end of a read, this device can accept either acknowledge (ack) or no acknowledge (nack) from the master (no acknowledge is typically used as a signal for the slave that the master has read its last byte). it takes this device 125 ms to measure the temperature. refer to timing diagrams figure 9 to figure 12 for how to program the device. fig 8. how SE97 responds to smbus alert response address 0 0 0 1 1 a2 alert response address 1 1 0 0 s 0 0 0 start bit read acknowledge 002aac685 a1 a0 0 1 p device address no acknowledge stop bit host nack and sends a stop bit slave acknowledges and sends its slave address. the last bit of slave address is hard coded '0'. master sends a start bit, ara and a read command host detects smbus alert 1 a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 9. smbus/i 2 c-bus write to the pointer register 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write register address wa s start ack by device p stop a ack by device 002aab308
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 14 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 10. smbus/i 2 c-bus write to the pointer register followed by a write data word 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write write register address wa s start by host ack by device a ack by device (cont.) (cont.) 002aab412 123456789123456789 scl d15 d14 d13 d12 d11 d10 d9 sda d7 d6 d5 d4 d3 d2 d1 d0 most significant byte data least significant byte data a by host ack by device p stop by host d8 a ack by device a = ack = acknowledge bit. a = nack = no acknowledge bit. w = write bit = 0. r = read bit = 1. fig 11. smbus/i 2 c-bus write to pointer register followed by a repeated start and an immediate data word read 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write read register address wa s start by host ack by device a ack by device (cont.) (cont.) 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra sr repeated start by host ack by device (cont.) (cont.) 002aac686 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop by host a nack by host
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 15 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v a = ack = acknowledge bit. a = nack = no acknowledge bit. w = write bit = 0. r = read bit = 1. fig 12. smbus/i 2 c-bus word read from register with a pre-set pointer 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra ack by device (cont.) (cont.) 002aac687 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop nack by host s start by host a
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 16 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.10 eeprom operation the 2-kbit eeprom is organized as either 256 bytes of 8 bits each (byte mode), or 16 pages of 16 bytes each (page mode). accessing the eeprom in byte mode or page mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported. communication with the eeprom is via the 2-wire serial i 2 c-bus or smbus. figure 13 provides an overview of the eeprom partitioning. the eeprom can be read over voltage range 1.7 v to 3.6 v, but all write operations must be done 3.0 v to 3.6 v. 7.10.1 write operations 7.10.1.1 byte write in byte write mode the master creates a start condition and then broadcasts the slave address, byte address, and data to be written. the slave acknowledges all 3 bytes by pulling down the sda line during the ninth clock cycle following each byte. the master creates a stop condition after the last ack from the slave, which then starts the internal write operation (see figure 14 ). during internal write, the slave will ignore any read/write request from the master. fig 13. eeprom partitioning ffh 80h 7fh 0fh 00h 00h 01h 07h ? 1 page or 16 bytes 8 pages or 128 bytes 16 pages or 256 bytes no write protect write protect by software 002aac812 fig 14. byte write timing 002aab246 0 1 0 a2 a1 a0 0 a s 1 a p slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda stop condition; write to the memory is performed data data a acknowledge from slave
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 17 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.10.1.2 page write the SE97 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. the page is selected by the four most signi?cant bits (msb) of the address byte presented to the device after the slave address, while the four least signi?cant bits (lsb) point to the byte within the page. by loading more than one data byte into the device, up to an entire page can be written in one write cycle (see figure 15 ). the internal byte address counter will increment automatically after each data byte. if the master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around fashion within the selected page. the internal write cycle is started following the stop condition created by the master. 7.10.1.3 acknowledge polling acknowledge polling can be used to determine if the SE97 is busy writing or is ready to accept commands. polling is implemented by sending a selective read command (described in section 7.10.3 read oper ations ) to the device. the SE97 will not acknowledge the slave address as long as internal write is in progress. 7.10.2 memory protection the lower half (the ?rst 128 bytes) of the memory can be write protected by special eeprom commands without an external control pin. the SE97 features three types of memory write protection instructions, and three respective read protection instructions. the level of write-protection (set or clear) that has been de?ned using these instructions remained de?ned even after power cycle. the memory protection commands are: ? permanent write protection (pwp) ? reversible write protection (rwp) ? clear write protection (cwp) ? read permanent write protection (rpwp) ? read reversible write protection (rrwp) ? read clear write protection (rcwp) fig 15. page write timing 0 1 0 a2 a1 a0 0 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda data to memory data n a acknowledge from slave 002aab247 p stop condition; write to the memory is performed data to memory data n + 15 a acknowledge from slave
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 18 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v t ab le 5 is the summary for normal and memory protection instructions. [1] the most signi?cant bit, bit 7, is sent ?rst. [2] a0, a1, and a2 are compared against the respective external pins on the SE97. [3] v i(ov) ranges from 7.8 v to 10 v. this special eeprom command consists of a unique 4-bit ?xed address (0110b) and the voltage level applied on the 3-bit hardware address. normally, to address the memory array, the 4-bit ?xed address is 1010b. to access the memory protection settings, the 4-bit ?xed address is 0110b. figure 16 and figure 17 show the write and read protection sequence, respectively. up to eight memory devices can be connected on a single i 2 c-bus. each one is given a 3-bit on the hardware selectable address (a2, a1, a0) inputs. the device only responds when the 4-bit ?xed and hardware selectable bits are matched. the 8th bit is the read/write bit. this bit is set to 1 or 0 for read and write protection, respectively. the corresponding device acknowledges during the ninth bit time when there is a match on the 7-bit address. the device does not acknowledge when there is no match on the 7-bit address or when the device is already in permanent write protection mode and is programmed with any write protection instructions (i.e., pwp, rwp, cwp). table 5. eeprom commands summary command fixed address hardware selectable address r/ w bit 7 [1] bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 normal eeprom read/write 1010a2a1a0r/ w reversible write protection (rwp) 0110v ss v ss v i(ov) [3] 0 clear reversible write protection (crwp) 0110v ss v dd v i(ov) [3] 0 permanent write protection (pwp) [2] 0110a2a1a00 read rwp 0110v ss v ss v i(ov) [3] 1 read crwp 0110v ss v dd v i(ov) [3] 1 read pwp 0110a2a1a01 x = dont care (1) refer to t ab le 6 regarding the exact state of the acknowledge bit. fig 16. software write protect (write) 1 1 0 a2 a1 a0 0 a s 0 a slave address (memory) start condition r/w acknowledge (1) from slave acknowledge (1) from slave dummy byte address sda dummy data a acknowledge (1) from slave 002aab356 p stop condition xxxxxxxx xxxxxxxx
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 19 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.10.2.1 permanent write protection (pwp) if the software write-protection has been set with the pwp instruction, the ?rst 128 bytes of the memory are permanently write-protected. this write-protection cannot be cleared by any instruction, or by power-cycling the device. also, once the pwp instruction has been successfully executed, the device no longer acknowledges any instruction (with 4-bit ?xed address of 0110b) to access the write-protection settings. 7.10.2.2 reversible write protection (rwp) and clear reversible write protection (crwp) if the software write-protection has been set with the rwp instruction, it can be cleared again with a crwp instruction. the two instructions, rwp and crwp have the same format as a byte write instruction, but with a different setting for the hardware address pins (as shown in t ab le 5 ). like the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents are all dont care ( figure 16 ). another difference is that the voltage, v i(ov) , must be applied on the a0 pin, and speci?c logical levels must be applied on the other two (a1 and a2), as shown in t ab le 5 . x = dont care (1) refer to t ab le 7 regarding the exact state of the acknowledge bit. fig 17. software write protect (read) 1 1 0 a2 a1 a0 1 a s 0 a slave address (memory) start condition r/w acknowledge (1) from slave no acknowledge (1) from slave dummy byte address sda dummy data a no acknowledge (1) from slave 002aac644 p stop condition xxxxxxxx xxxxxxxx table 6. acknowledge when writing data or de?ning write protection instructions with r/ w bit = 0. status instruction ack address ack data byte ack write cycle (t cy(w) ) permanently protected pwp, rwp or crwp nack not signi?cant nack not signi?cant nack no page or byte write in lower 128 bytes ack address ack data nack no protected with rwp rwp nack not signi?cant nack not signi?cant nack no crwp ack not signi?cant ack not signi?cant ack yes pwp ack not signi?cant ack not signi?cant ack yes page or byte write in lower 128 bytes ack address ack data nack no not protected pwp or rwp ack not signi?cant ack not signi?cant ack yes crwp ack not signi?cant ack not signi?cant ack no page or byte write ack address ack data ack yes
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 20 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.10.2.3 read permanent write protection (rpwp), read reversible write protection (rrwp), and read clear reversible write protection (rcrwp) read pwp, rwp, and crwp allow the SE97 to be read in write protection mode. the instruction format is the same as that of the write protection except that the 8 th bit, r/ w, is set to 1. figure 17 shows the instruction format, while t ab le 7 shows the responses when the instructions are issued. 7.10.3 read operations 7.10.3.1 current address read in standby mode, the SE97 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. if the previous byte was the last byte in memory, then the address counter will point to the ?rst memory byte, and so on. if the SE97 decodes a slave address with a 1 in the r/ w bit position ( figure 18 ), it will issue an acknowledge in the ninth clock cycle and will then transmit the data byte being pointed at by the address counter. the master can then stop further transmission by issuing a no acknowledge on the ninth bit then followed by a stop condition. 7.10.3.2 selective read the read operation can also be started at an address different from the one stored in the address counter. the address counter can be initialized by performing a dummy write operation ( figure 19 ). the start condition is followed by the slave address (with the r/ w bit set to 0) and the desired byte address. instead of following-up with data, the master then issues a second start, followed by the current address read sequence, as described in section 7.10.3.1 . table 7. acknowledge when reading the write protection instructions with r/ w bit = 1. status instruction ack address ack data byte ack permanently protected rpwp, rrwp or rcrwp nack not signi?cant nack not signi?cant nack protected with rwp rrwp nack not signi?cant nack not signi?cant nack rcrwp ack not signi?cant nack not signi?cant nack rpwp ack not signi?cant nack not signi?cant nack not protected rpwp, rrwp or rcrwp ack not signi?cant nack not signi?cant nack fig 18. current address read timing 0 1 0 a2 a1 a0 1 a s 1 slave address (memory) start condition r/w acknowledge from slave data from memory sda 002aab251 p stop condition no acknowledge from master a
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 21 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.10.3.3 sequential read if the master acknowledges the ?rst data byte transmitted by the SE97, then the device will continue transmitting as long as each data byte is acknowledged by the master ( figure 20 ). if the end of memory is reached during sequential read, the address counter will wrap around to the beginning of memory, and so on. sequential read works with either immediate address read or selective read, the only difference being the starting byte address. fig 19. selective read timing 0 1 0 a2 a1 a0 0 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda 002aac901 p stop condition data from memory a no acknowledge from master 0 1 0 a2 a1 a0 s 1 slave address (memory) start condition 1 a r/w acknowledge from slave fig 20. sequential read timing 0 1 0 a2 a1 a0 1 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from master data from memory sda data from memory data n + 1 a acknowledge from master 002aab253 p stop condition data from memory data n + x a no acknowledge from master data n
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 22 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7.11 hot plugging the SE97 can be used in hot plugging applications. internal circuitry prevents damaging current back?ow through the device when it is powered down, but with the i 2 c-bus, event or address pins still connected. the open-drain sda and event pins (scl and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver con?ict and bus contention. the 50 ns noise ?lter will ?lter out any insertion glitches from the state machine, which is very robust and not prone to false operation. the device needs a proper power-up sequence to reset itself, not only for the device i 2 c-bus and i/o initial states, but also to load speci?c pre-de?ned data or calibration data into its operational registers. the power-up sequence should occur correctly with a fast ramp rate and the i 2 c-bus active. the SE97 might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. if the scl line is held low, the part will not exit the power-on reset mode since the part is held in reset until scl is released. 8. register descriptions 8.1 register overview this section describes all the registers used in the SE97. the registers are used for latching the temperature reading, storing the low and high temperature limits, con?guring, the hysteresis threshold and the adc, as well as reporting status. the device uses the pointer register to access these registers. read registers, as the name implies, are used for read only, and the write registers are for write only. any attempt to read from a write-only register will result in reading 0s. writing to a read-only register will have no effect on the read even though the write command is acknowledged. the pointer register is an 8-bit register. all other registers are 16-bit. a write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power. table 8. register summary address (hex) default state (hex) register name n/a n/a pointer register 00h 0017h capability register (b grade = 0017h) 01h 0000h con?guration register 02h 0000h upper boundary alarm trip register 03h 0000h lower boundary alarm trip register 04h 0000h critical alarm trip register 05h n/a temperature register 06h 1131h manufacturer id register 07h a200h device id/revision register 08h to 21h 0000h reserved registers 22h 0000h smbus register 23h to ffh 0000h reserved registers
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 23 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.2 capability register (00h, 16-bit read-only) [1] the SE97 a0 pin can support up to 10 v, but the ?nal die was already taped out before the jc42.4 ballot 1435.00 register change could be implemented. bit 5 is changed from 0 to 1 on the future 1.7 v to 3.6 v SE97b. table 9. capability register (address 00h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu default 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rfu vhv tres wrng hacc bcap default 000 [1] 10111 access rrrrrrrr table 10. capability register (address 00h) bit description bit symbol description 15:6 rfu reserved for future use; must be zero. 5 vhv high voltage standoff for pin a0. 0 default 1 this part can support a voltage up to 10 v on the a0 pin to support jc42.4 ballot 1435.00. 4:3 tres temperature resolution. 10 0.125 c lsb (11-bit) 2 wrng wider range. 1 can read temperatures below 0 c and set sign bit accordingly 1 hacc higher accuracy (set during manufacture). 1 b grade accuracy 0 bcap basic capability. 1 has alarm and critical trips interrupt capability
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 24 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.3 con?guration register (01h, 16-bit read/write) table 11. con?guration register (address 01h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu hen shmd default 00000000 access rrrrrr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol ctlb awlb cevnt estat eoctl cvo ep emd default 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 12. con?guration register (address 01h) bit description bit symbol description 15:1 1 rfu reserved for future use; must be 0. 10:9 hen hysteresis enable. 00 disable hysteresis (default) 01 enable hysteresis at 1.5 c 10 enable hysteresis at 3 c 11 enable hysteresis at 6 c when enabled, hysteresis is applied to temperature movement around trigger points. for example, consider the behavior of the above alarm window bit (bit 14 of the temperature register) when the hysteresis is set to 3 c. as the temperature rises, bit 14 will be set to 1 (temperature is above the alarm window) when the temperature register contains a value that is greater than the value in the alarm temperature upper boundary register. if the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the alarm temperature upper boundary register minus 3 c. (refer to figure 7 and t ab le 13 ). similarly, the below alarm window bit (bit 13 of the temperature register) will be set to 0 (temperature is equal to or above the alarm window lower boundary trip register) when the value in the temperature register is equal to or greater than the value in the alarm temperature lower boundary register. as the temperature decreases, bit 13 will be set to 1 when the value in the temperature register is equal to or less than the value in the alarm temperature lower boundary register minus 3 c. note that hysteresis is also applied to event pin functionality. when either of the critical trip or alarm window lock bits is set, these bits cannot be altered until unlocked.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 25 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8 shmd shutdown mode. 0 enabled temperature sensor (default) 1 disabled temperature sensor when shut down, the thermal sensor diode and adc are disabled to save power, no events will be generated. when either of the critical trip or alarm window lock bits is set, this bit cannot be set until unlocked. however, it can be cleared at any time. remark: smbus time-out works over the entire supply range of 1.7 v to 3.6 v unless the shutdown bit (shmd) is set and turns off the oscillator. ? the eeprom read works over the entire supply range of 1.7 v to 3.6 v whether or not shmd is set because it does not need oscillator to function. there is no undervoltage lockout, the device no longer responds at some voltage below 1.7 v. ? eeprom write works over the supply range of 3.0 v to 3.6 v, but not if shmd is set since the oscillator is needed to write to eeprom. there is an undervoltage lockout around 2.7 v that disables the rrprom write operation. ? thermal sensor is operational over the supply range of 3.0 v to 3.6 v, but not if shmd is set since the oscillator is needed. there is an undervoltage lockout around 2.7 v that disables the temp sensor. thermal sensor auto turn-off feature: it was determined during testing of the SE97tp on 5 may 2008 that the thermal sensor auto turn-off feature was not compatible with the jedec power supply maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was disabled for all SE97 samples/production devices tested after 6 may (wk 0818 date code is when the devices were assembled). if there is a slow ramp rate on the supply voltage to 3.3 v the SE97 would be ee read only and not thermal sensor. this is due to a feature integrated into the device to automatically turn off the oscillator and place the thermal sensor in shutdown if the SE97 was being used in so-dimm in notebook applications at 1.8 v to reduce the power consumption on the battery. the feature counts for 30 ms ( 5 ms) after the oscillator starts working (around 1.2 v to 1.7 v) and if at 30 ms the voltage is greater than 2.4 v, the oscillator is left on and the thermal sensor functions as normal. but if the voltage is less than 2.4 v at 30 ms, the oscillator is turned off and the SE97 will think the part is in spd only mode defaulting to the oscillator and thermal sensor disabled (shmd shutdown mode bit 8 = 1). the oscillator and thermal sensor can be re-enabled by writing a logic 0 to shmd. it is important in rdimm/server applications that the thermal sensor is working as the default condition since the thermal sensor needs to be compatible with the jedec power supply ramp rate (maximum ramp rate is 70 ms to 100 ms) so the thermal sensor auto turn-off feature was disabled starting on 6 may 2008 by changing a programmable bit on the device during ?nal test. there is no change in performance of the SE97 with this feature turned off and was veri?ed during characterization. there is no way to read the SE97 registers via the i 2 c-bus to determine if the thermal sensor auto turn-off feature is enabled or disabled. this is set in a factory only register. you need to check the date code or do an operational test (e.g., run up to < 2.4 v, hold, then go to 3.3 v, then read shmd bit 8 in the con?guration register to see if it is set to logic 0 (e.g., oscillator running = feature disabled) or logic 1 (e.g., oscillator turned off = feature enabled)). the thermal sensor auto turn-off feature is active in all package options prior to wk 0818. the SE97tp and SE97tl were not yet released to production so there is a clear line at release/orderable devices versus samples with this feature disabled in all production devices. table 12. con?guration register (address 01h) bit description continued bit symbol description
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 26 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 7 ctlb critical trip lock bit. 0 critical alarm trip register is not locked and can be altered (default) 1 critical alarm trip register settings cannot be altered this bit is initially cleared. when set, this bit will return a 1, and remains locked until cleared by internal power-on reset. this bit can be written with a single write and do not require double writes. 6 awlb alarm window lock bit. 0 upper and lower alarm trip registers are not locked and can be altered (default) 1 upper and lower alarm trip registers setting cannot be altered this bit is initially cleared. when set, this bit will return a 1 and remains locked until cleared by internal power-on reset. this bit can be written with a single write and does not require double writes. 5 cevnt clear event (write only). 0 no effect (default) 1 clears active event in interrupt mode. writing to this register has no effect in comparator mode. when read, this register always returns zero. 4 estat event status (read only). 0 event output condition is not being asserted by this device (default) 1 event output pin is being asserted by this device due to alarm window or critical trip condition the actual event causing the event can be determined from the read temperature register. interrupt events can be cleared by writing to the clear event bit (cevnt). writing to this bit will have no effect. 3 eoctl event output control. 0 event output disabled (default) 1 event output enabled when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 2 cvo critical event only. 0 event output on alarm or critical temperature event (default) 1 event only if temperature is above the value in the critical temperature register when the critical trip or alarm window lock bit is set, this bit cannot be altered until unlocked. ? advisory note: C jedec speci?cation requires only the alarm window lock bit to be set. C work-around: clear both critical trip and alarm window lock bits. C future 1.7 v to 3.6 v SE97b will require only the alarm window lock bit to be set. 1ep event polarity. 0 active low (default) 1 active high. when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. table 12. con?guration register (address 01h) bit description continued bit symbol description
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 27 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 0 emd event mode. 0 comparator output mode (default) 1 interrupt mode when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. table 12. con?guration register (address 01h) bit description continued bit symbol description table 13. hysteresis enable action below alarm window bit (bit 13) above alarm window bit (bit 14) above critical trip bit (bit 15) temperature slope threshold temperature temperature slope threshold temperature temperature slope threshold temperature sets falling t trip(l) - t hys rising t trip(u) rising t th(crit) clears rising t trip(l) falling t trip(u) - t hys falling t th(crit) - t hys fig 21. hysteresis: how it works 002aac799 current temperature time temperature set clear clear set clear clear set clear below alarm window (register 05h; bit 13 = baw bit) above alarm window (register 05h; bit 14 = aaw bit) above critical trip (register 05h; bit 15 = act bit) lower alarm threshold upper alarm threshold critical alarm threshold hysteresis hysteresis hysteresis
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 28 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.4 temperature format the temperature data from the temperature read back register is an 11-bit 2s complement word with the least signi?cant bit (lsb) equal to 0.125 c (resolution). ? a value of 019ch will represent 25.75 c ? a value of 07c0h will represent 124 c ? a value of 1e64h will represent - 25.75 c. the unused lsb (bit 0) is set to 0. bit 11 will have a resolution of 128 c. the upper 3 bits of the temperature register indicate trip status based on the current temperature, and are not affected by the status of the event output. t ab le 14 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b. table 14. degree celsius and temperature data register temperature content of temperature data register status bits = 000b status bits = 111b binary hex binary hex +125 c 000 0 01111101 000 0 07d0h 111 0 01111101 000 0 e7d0h +25 c 000 0 00011001 000 0 0190h 111 0 00011001 000 0 e190h +1 c 000 0 00000001 000 0 0010h 111 0 00000001 000 0 e010h +0.25 c 000 0 00000000 010 0 0004h 111 0 00000000 010 0 e004h +0.125 c 000 0 00000000 001 0 0002h 111 0 00000000 001 0 e002h 0 c 000 0 00000000 000 0 0000h 111 0 00000000 000 0 e000h - 0.125 c 000 1 11111111 111 0 1ffeh 111 1 11111111 111 0 fffeh - 0.25 c 000 1 11111111 110 0 1ffch 111 1 11111111 110 0 fffch - 1 c 000 1 11111111 000 0 1ff0h 111 1 11111111 000 0 fff0h - 20 c 000 1 11110100 000 0 1f40h 111 1 11110100 000 0 ff40h - 25 c 000 1 11100111 000 0 1e70h 111 1 11100111 000 0 fe70h - 55 c 000 1 11001001 000 0 1c90h 111 1 11001001 000 0 fc90h
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 29 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.5 temperature trip point registers 8.5.1 upper boundary alarm trip register (16-bit read/write) the value is the upper threshold temperature value for alarm mode. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid super?uous interrupt activity. table 15. upper boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign ubt default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ubt rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 16. upper boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 ubt upper boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 30 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.5.2 lower boundary alarm trip register (16-bit read/write) the value is the lower threshold temperature value for alarm mode. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid super?uous interrupt activity. 8.5.3 critical alarm trip register (16-bit read/write) the value is the critical temperature. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. table 17. lower boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign lbt default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lbt rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 18. lower boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 lbt lower boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0 table 19. lower boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign ct default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ct rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 20. critical alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 ct critical alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 31 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.6 temperature register (16-bit read-only) table 21. temperature register bit allocation bit 15 14 13 12 11 10 9 8 symbol act aaw baw sign temp default 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol temp rfu default 00000000 access rrrrrrrr table 22. temperature register bit description bit symbol description 15 act above critical trip. increasing t amb : 0 t amb t trip(u) decreasing t amb : 0 t amb t trip(u) - t hys 1 t amb >t trip(u) - t hys 13 baw below alarm window. increasing t amb : 0 t amb 3 t trip(l) 1 t amb SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 32 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.7 manufacturers id register (16-bit read-only) the SE97 manufacturers id register is intended to match nxp semiconductors pci sig (1131h). 8.8 device id register the SE97 device id is a1h. the device revision varies by device. [1] 00 for SE97pw, SE97tk (original). 01 for SE97tl, SE97tp (improved v por and event i ol ). table 23. manufacturers id register bit allocation bit 15 14 13 12 11 10 9 8 symbol manufacturer id default 00010001 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol (continued) default 00110001 access rrrrrrrr table 24. device id register bit allocation bit 15 14 13 12 11 10 9 8 symbol device id default 10100010 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol device revision default 000000 [1] [1] access rrrrrrrr
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 33 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 8.9 smbus register table 25. smbus time-out register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu default 0 0000000 access r rrrrrrr bit 7 6 5 4 3 2 1 0 symbol stmout rfu salrt default 0 0000000 access r/wrrrrrrr/w table 26. smbus time-out register bit description bit symbol description 15:8 rfu reserved; always 0 7 stmout smbus time-out. 0 smbus time-out is enabled (default) 1 disable smbus time-out when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 6:1 rfu reserved; always 0 0 salrt smbus alert response address (ara). 0 smbus ara is enabled (default) 1 disable smbus ara when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked.
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 34 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 9. application design-in information in a typical application, the SE97 behaves as a slave device and interfaces to a bus master (or host) via the scl and sda lines. the event output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers. the a0, a1 and a2 pins are directly connected to v dd or v ss without any pull-up resistors. the sda and scl serial interface pins are open-drain i/os that require pull-up resistors, and are able to sink a maximum of 3 ma with a voltage drop less than 0.4 v. typical pull-up values for scl and sda are 10 k w , but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. fig 22. typical application showing SE97 interfacing with 3.3 v host 002aab354 host controller SE97 a0 a1 a2 scl sda event v dd 10 k w (3 ) v ss slave master 3.3 v fig 23. SE97 interfacing with 1.1 v host controller 002aad262 host controller SE97 a0 a1 a2 scl sda event v dd 10 k w v ss 3.3 v 0.1 m f 10 k w pca9509 mother board 0.1 m f v cc(b) b2 b1 en v cc(a) a2 a1 10 k w 10 k w scl sda event 0.1 m f 1.1 v
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 35 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 9.1 SE97 in memory module application figure 24 shows the SE97 being placed in the memory module application. the SE97 is centered in the memory module to monitor the temperature of the dram and also to provide a 2-kbit eeprom as the serial presence detect (spd). in the event of overheating, the SE97 triggers the event output and the memory controller throttles the memory bus to slow the dram. the memory controller can also read the SE97 and watch the dram thermal behavior, taking preventive measures when necessary. 9.2 layout consideration the SE97 does not require any additional components other than the host controller to read its temperature. it is recommended that a 0.1 m f bypass capacitor between the v dd and v ss pins is located as close as possible to the power and ground pins for noise protection. 9.3 thermal considerations in general, self-heating is the result of power consumption and not a concern, especially with the SE97, which consumes very low power. in the event the sda and event pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 c. equation 1 is the formula to calculate the effect of self-heating: (1) where: d t = t j - t amb t j = junction temperature t amb = ambient temperature r th(j-a) = package thermal resistance v dd = supply voltage i dd(av) = average supply current fig 24. system application 002aac800 SE97 event dimm dram dram dram dram memory controller smbus cpu d tr th j - a () v dd i dd av () () v ol sda () i ol k sin () sda () () v ol event () i ol k sin () event () ++ [ ] =
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 36 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v v ol(sda) = low-level output voltage on pin sda v ol(event) = low-level output voltage on pin event i ol(sink)(sda) = sda output current low i ol(sink)event = event output current low calculation example: t amb (typical temperature inside the notebook) = 50 c i dd(av) = 400 m a v dd = 3.6 v maximum v ol(sda) = 0.4 v i ol(sink)(sda) = 1 ma v ol(event) = 0.4 v i ol(sink)event = 3 ma r th(j-a) of hvson8 = 56 c/w r th(j-a) of tssop8 = 160 c/w self heating due to power dissipation for hvson8 is: (2) self heating due to power dissipation for tssop8 is: (3) 10. limiting values d t 56 3.6 0.4 () 0.4 3 () 0.4 1 () ++ [] 56 c w 3.04 mw 0.17 c = = = d t 160 3.6 0.4 () 0.4 3 () 0.4 1 () ++ [] 160 c w 3.04 mv 0.49 c == = table 27. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.3 +4.2 v v n voltage on any other pin sda, scl, event pins - 0.3 +4.2 v v a0 voltage on pin a0 overvoltage input; a0 pin - 0.3 +12.5 v i sink sink current at sda, scl, event pins - 1 +50.0 ma t j(max) maximum junction temperature - 150 c t stg storage temperature - 65 +165 c
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 37 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 11. characteristics table 28. SE97 thermal sensor characteristics v dd = 3.0 v to 3.6 v; t amb = - 40 c to +125 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t lim(acc) temperature limit accuracy b grade; v dd = 3.3 v 10 % t amb =75 cto95 c - 1.0 < 0.5 +1.0 c t amb =40 c to 125 c - 2.0 < 1.0 +2.0 c t amb = - 40 c to +125 c - 3.0 < 2 +3.0 c t res temperature resolution - 0.125 - c t conv conversion period conversion time from stop bit to conversion complete - 100 120 ms e f(conv) conversion rate error percentage error in programmed data - 30 - +30 %
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 38 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v [1] high-voltage input voltage applied to pin a0 during rwp and crwp operations. the jedec speci?cation is 7 v (min.) and 10 v (max.), but since the SE97 eeprom write works only down to 3.0 v, the condition of v i(ov) >4.8v+v dd or > 4.8 v + 3.0 v was applied and the minimum voltage changed to 7.8 v. if v dd is 3.6 v then the minimum voltage is 8.4 v. table 29. dc characteristics v dd = 1.7 v to 3.6 v; t amb = - 40 c to +125 c; unless otherwise speci?ed. these speci?cations are guaranteed by design. symbol parameter conditions min typ max unit i dd(av) average supply current smbus inactive - 250 400 m a i sd(vdd) supply voltage shutdown mode current smbus inactive - 0.1 5.0 m a v ih high-level input voltage scl, sda; v dd = 3.0 v to 3.6 v 0.7 v dd -v dd +1 v v il low-level input voltage scl, sda; v dd = 3.0 v to 3.6 v - - 0.3 v dd v v ol1 low-level output voltage 1 v dd = 3.0 v; i ol = 3 ma - - 0.4 v v ol2 low-level output voltage 2 v dd = 1.7 v; i ol = 1.5 ma - - 0.5 v v i(ov) overvoltage input voltage pin a0; v i(ov) - v dd > 4.8 v [1] 7.8 - 10 v v por power-on reset voltage power supply rising - - 1.7 v power supply falling SE97pw, SE97tk 0.1 - - v SE97tl, SE97tp 0.6 - - v i ol(sink)event low-level output sink current on pin event v ol1 = 0.4 v SE97pw, SE97tk 2 - - ma SE97tl, SE97tp 6 - - ma i ol(sink)(sda) low-level output sink current on pin sda v ol2 = 0.5 v 3 - - ma i loh high-level output leakage current event; v oh =v dd - 1.0 - +1.0 m a i lih high-level input leakage current sda, scl; v i =v dd - 1.0 - +1.0 m a i lil low-level input leakage current sda, scl; v i =v ss - 1.0 - +1.0 m a a0, a1, a2; v i =v ss - 1.0 - +1.0 m a c i(scl/sda) scl and sda input capacitance - 5 10 pf i l leakage current on a0, a1, a2 - 1 - m a i pd pull-down current internal; a0, a1, a2 pins; v i = 0.3v dd to v dd - - 4.0 m a z il low-level input impedance pins a0, a1, a2; v i < 0.3v dd 30 - - k w z ih high-level input impedance pins a0, a1, a2 800 - - k w
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 39 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v i 2 c-bus and eeprom inactive. i 2 c-bus, temp sensor and eeprom inactive. fig 25. average supply current fig 26. shutdown supply current temp sensor and eeprom active. v dd = 3.0 v to 3.6 v. fig 27. average supply current during eeprom write fig 28. typical temperature accuracy v ol1 = 0.4 v. v ol1 = 0.4 v. fig 29. event output current SE97pw, SE97tk fig 30. event output current SE97tl, SE97tp 200 300 100 400 500 i dd(av) ( m a) 0 t amb ( c) - 40 120 80 040 002aac910 v dd = 3.6 v 3.0 v 1 3 5 i sd(vdd) ( m a) - 1 t amb ( c) - 40 120 80 040 002aac911 v dd = 3.6 v 3.0 v 200 500 400 300 600 i dd(av) ( m a) 002aac912 t amb ( c) - 40 120 80 040 v dd = 3.6 v 3.0 v - 2.0 3.5 - 3.5 t amb ( c) - 50 125 002aad769 100 75 50 25 0 - 25 2.0 t lim(acc) ( c) 0 - 1.0 1.0 2.0 8.0 i ol (ma) 0 t amb ( c) - 50 125 002aad258 100 75 50 25 0 - 25 6.0 4.0 v dd = 3.0 v to 3.6 v v dd = 1.7 v t amb ( c) - 50 125 002aad767 100 75 50 25 0 - 25 v dd = 3.7 v 3.3 v 2.9 v 1.7 v 10 20 30 i ol(sink)event (ma) 0
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 40 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v v ol2 = 0.6 v. v dd = 3.0 v to 3.6 v. fig 31. sda output current fig 32. conversion rate v dd = 3.0 v to 3.6 v. v dd = 3.0 v to 3.6 v. fig 33. conversion period fig 34. eeprom write cycle time for temp sensor conversion. v dd = 3.0 v to 3.6 v. for eeprom read operation. v dd = 1.7 v to 3.6 v. fig 35. average power-on threshold voltage fig 36. average power-on threshold voltage t amb ( c) - 40 120 80 040 002aac907 v dd = 3.6 v 3.0 v 10 15 5 20 25 i ol(sink)(sda) (ma) 0 t amb ( c) - 40 120 80 040 002aac908 9 11 7 13 15 5 conversion rate (conv/s) 60 120 100 80 140 t conv (ms) 002aac909 t amb ( c) - 40 120 80 040 3 4 5 t cy(w) (ms) 2 t amb ( c) - 40 120 80 040 002aac902 2.4 2.6 2.2 2.8 3.0 v th (v) 2.0 t amb ( c) - 40 120 80 040 002aac903 1.2 1.4 1.6 v th (v) 1.0 t amb ( c) - 40 120 80 040 002aac904
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 41 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v v dd = 3.0 v to 3.6 v. from 25 c (air) to 120 c (oil bath). (1) tssop8 (2) hvson8, hwson8, hxson8 v dd = 3.3 v + 150 mv (p-p); 0.1 m f ac coupling capacitor; no decoupling capacitor; t amb =25 c. fig 37. package thermal response fig 38. temperature error versus power supply noise frequency 40 80 120 thermal response (%) 0 time (s) 05 4 23 1 002aac905 (1) (2) noise frequency (hz) 10 2 10 8 10 7 10 6 10 3 10 5 10 4 002aac914 1 3 5 temp error ( c) - 1
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 42 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v [1] minimum clock frequency is 0 khz if smbus time-out is disabled. [2] delay from sda stop to sda start. [3] a device must internally provide a hold time of at least 200 ns for sda signal (referenced to the v ih(min) of the scl signal) to bridge the unde?ned region of the falling edge of scl. [4] delay from scl high-to-low transition to sda edges. [5] delay from scl low-to-high transition to restart sda. [6] delay from sda start to ?rst scl high-to-low transition. [7] these parameters tested initially and after a design or process change that affects the parameter. [8] t pu(r) and t pu(w) are the delays required from the time v dd is stable until the speci?ed operation can be initiated. table 30. smbus ac characteristics v dd = 1.7 v to 3.6 v; t amb = - 40 c to +125 c; unless otherwise speci?ed. these speci?cations are guaranteed by design. the ac speci?cations fully meet or exceed smbus 2.0 speci?cations, but allow the bus to interface with the i 2 c-bus from dc to 400 khz. symbol parameter conditions standard mode fast mode unit min max min max f scl scl clock frequency 10 [1] 100 10 [1] 400 khz t high high period of the scl clock 70 % to 70 % 4000 - 600 - ns t low low period of the scl clock 30 % to 30 % 4700 - 1300 - ns t to(smbus) smbus time-out time low period to reset smbus 25 35 25 35 ms t r rise time of both sda and scl signals - 1000 20 300 ns t f fall time of both sda and scl signals - 300 - 300 ns t su;dat data set-up time 250 - 100 - ns t h(i)(d) data input hold time [2] [3] 0-0-ns t hd;dat data hold time [4] 200 3450 200 900 ns t su;sta set-up time for a repeated start condition [5] 4700 - 600 - ns t hd;sta hold time (repeated) start condition 30 % of sda to 70 % of scl [6] 4000 - 600 - ns t su;sto set-up time for stop condition 4000 - 600 - ns t buf bus free time between a stop and start condition [2] 4700 - 1300 - ns t sp pulse width of spikes that must be suppressed by the input ?lter -50-50ns t vd;dat data valid time from clock 200 - 200 - ns t f(o) output fall time - - - 250 ns t por power-on reset pulse time power supply falling 0.5 - 0.5 - m s eeprom power-up timing [7] t pu(r) read power-up time [8] -1-1ms t pu(w) write power-up time [8] -1-1ms write cycle limits t cy(w) write cycle time [9] -10-10ms
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 43 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v [9] the write cycle time is the time elapsed between the stop command (following the write instruction) and the completion of the internal write cycle. during the internal write cycle, sda is released by the slave and the device does not acknowledge external command s. s = start condition p = stop condition fig 39. ac waveforms 002aae750 t low sda p s t buf t hd;sta t r t hd;dat t high t su;dat t su;sta t hd;dat s p t su;sto v ih v il v ih v il scl sda scl t su;sto v ih v il v ih v il t w stop condition start condition t su;sta write cycle t f
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 44 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 12. package outline fig 40. package outline sot530-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.13 3.1 2.9 4.5 4.3 0.65 6.5 6.3 0.70 0.35 8 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.5 sot530-1 mo-153 00-02-24 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm sot530-1 1.1 pin 1 index
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 45 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v fig 41. package outline sot908-1 (hvson8) 0.5 0.2 1 0.05 0.00 a 1 e h b unit d (1) y e 1.5 e 1 references outline version european projection issue date iec jedec jeita mm 3.1 2.9 cd h 1.65 1.35 y 1 3.1 2.9 2.25 1.95 0.3 0.2 0.05 0.1 dimensions (mm are the original dimensions) sot908-1 mo-229 e (1) 0.5 0.3 l 0.1 v 0.05 w sot908-1 hvson8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm a (1) max. 05-09-26 05-10-05 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. x terminal 1 index area b a d e detail x a a 1 c c y c y 1 exposed tie bar (4 ) exposed tie bar (4 ) b terminal 1 index area e 1 e a c b v m c w m e h d h l 14 5 8 0 1 2 mm scale
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 46 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v fig 42. package outline sot1052-1 (hxson8) references outline version european projection issue date iec jedec jeita sot1052-1 mo-229 sot1052-1 note 1. dimension a is including plating thickness. the package footprint is compatible with jedec mo229 dimensions (mm are the original dimensions) hxson8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm unit mm max nom min 0.5 0.04 2.1 2.0 1.9 1.6 1.4 0.5 3.1 3.0 2.9 1.6 1.4 0.45 0.35 0.3 0.2 0.1 0.05 0.05 a (1) a 1 b d d 1 e e 1 e l v y y 1 0 1 2 mm scale terminal 1 index area d h e 1/2 e e h l 85 14 b a d e terminal 1 index area x b a b v m detail x a a 1 c y 1 c y (8 ) 08-01-11 08-03-11
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 47 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v fig 43. package outline sot1069-1 (hwson8) references outline version european projection issue date iec jedec jeita sot1069-1 mo-229 sot1069-1 note 1. dimension a is including plating thickness. the package footprint is compatible with jedec mo229 dimensions (mm are the original dimensions) hwson8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm unit mm max nom min 0.8 0.04 2.1 2.0 1.9 1.6 1.4 0.5 3.1 3.0 2.9 1.6 1.4 0.45 0.35 0.3 0.2 0.1 0.05 0.05 a (1) a 1 b d d 1 e e 1 e l v y y 1 0 1 2 mm scale terminal 1 index area d h e 1/2 e e h l 85 14 b a d e terminal 1 index area x b a b v m detail x a a 1 c y 1 c y (8 ) 08-06-11 08-07-10
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 48 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 49 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 44 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 31 and 32 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 44 . table 31. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 32. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 50 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 44. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 33. abbreviations acronym description adc analog-to-digital converter ara alert response address cdm charged-device model cmos complementary metal-oxide semiconductor cpu central processing unit ddr double data rate dimm dual in-line memory module dram dynamic random access memory ecc error-correcting code eeprom electrically erasable programmable read-only memory esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus lsb least signi?cant bit mm machine model msb most signi?cant bit pc personal computer pcb printed-circuit board por power-on reset
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 51 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 15. revision history rdimm registered dual in-line memory module smbus system management bus so-dimm small outline dual in-line memory module spd serial presence detect table 33. abbreviations continued acronym description table 34. revision history document id release date data sheet status change notice supersedes SE97_5 20090806 product data sheet - SE97_4 modi?cations: ? section 1 gener al descr iption , 7 th paragraph: deleted 5 th sentence ? section 2.1 gener al f eatures : C 1 st bullet item: changed from so-dimm to tse 2002b3 dimm 0.5 c (typ.) between 75 c and 95 c C 3 rd bullet item: changed from 3.0 m a (max.) to 5.0 m a (max.) C 8 th bullet item: appended (jedec pson8 vced-3) ? t ab le 1 order ing inf or mation , t ab le note [2] re-written ? section 7.3.2.1 alar m windo w : C 1 st advisory noti?cation, competitor device: appended (cevnt) to end of phrase C 1 st advisory noti?cation, work-around: appended (cevnt) to end of phrase C 2 nd advisory noti?cation, competitor devices: changed from ... when new upper or lower and event bit 3 (eoctl) are set ... to when new upper or lower alarm windows and the event output are set ... C 2 nd advisory noti?cation, work-around: appended (eoctl = 1) to end of phrase ? section 7.3.2.2 cr itical tr ip C 1 st paragraph, last sentence: changed from ... through the clear event bit ... to ... through the clear event bit (cevnt) ... C advisory noti?cation, competitor devices: re-written C advisory noti?cation, work-around: changed from wait at least 125 ms before enabling event output, intel will change nehalem bios so that t th(crit) is set for more than 125 ms before event bit 3 (eoctl) is enabled and event value is checked. to wait at least 125 ms before enabling event output (eoctl = 1), intel will change nehalem bios so that t th(crit) is set for more than 125 ms before event output is enabled and event value is checked. ? section 7.7 smbus time-out : C 1 st paragraph, 2 nd sentence changed from ... holds scl low more than 35 ms to ... holds scl low between 25 ns and 35 ns C added 2 nd remark ? section 7.8 smbus aler t response address (ara) : added 2 nd remark ? t ab le 12 con? gur ation register (address 01h) bit descr iption , bit 8, shmd: added remark and 3 bullet items ? t ab le 29 dc char acter istics : C i dd(av) : removed condition v dd = 3.0 v to 3.6 v C i dd(av) : removed sub-row with condition v dd = 1.7 v C i sd(vdd) : changed max value from 3 m a to 5.0 m a
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 52 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v modi?cations: (continued) ? t ab le 30 smbus a c char acter istics replaced in its entirety ? (old) figure 39 de?nition of timing for f/s-mode devices on the i 2 c-bus replaced with (new) figure 39 a c w a v ef or ms SE97_4 20090130 product data sheet - SE97_3 SE97_3 20080715 product data sheet - SE97_2 SE97_2 20071012 product data sheet - SE97_1 SE97_1 20070524 objective data sheet - - table 34. revision history continued document id release date data sheet status change notice supersedes
SE97_5 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 05 6 august 2009 53 of 54 nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors SE97 ddr memory module temp sensor with integrated spd, 3.3 v ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 6 august 2009 document identifier: SE97_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 general features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 temperature sensor features . . . . . . . . . . . . . . 2 2.3 serial eeprom features . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 serial bus interface . . . . . . . . . . . . . . . . . . . . . . 6 7.2 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 event output condition . . . . . . . . . . . . . . . . . . 7 7.3.1 event pin output voltage levels and resistor sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3.2 event thresholds . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.1 alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.2 critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.3 event operation modes . . . . . . . . . . . . . . . . . . 10 7.3.3.1 comparator mode. . . . . . . . . . . . . . . . . . . . . . 10 7.3.3.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 10 7.4 conversion rate. . . . . . . . . . . . . . . . . . . . . . . . 11 7.4.1 what temperature is read when conversion is in progress . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 power-up default condition . . . . . . . . . . . . . . . 11 7.6 device initialization . . . . . . . . . . . . . . . . . . . . . 11 7.7 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . 12 7.8 smbus alert response address (ara) . . . . . 12 7.9 smbus/i 2 c-bus interface . . . . . . . . . . . . . . . . 13 7.10 eeprom operation . . . . . . . . . . . . . . . . . . . . 16 7.10.1 write operations . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10.1.3 acknowledge polling . . . . . . . . . . . . . . . . . . . . 17 7.10.2 memory protection . . . . . . . . . . . . . . . . . . . . . 17 7.10.2.1 permanent write protection (pwp) . . . . . . . . 19 7.10.2.2 reversible write protection (rwp) and clear reversible write protection (crwp) . . 19 7.10.2.3 read permanent write protection (rpwp), read reversible write protection (rrwp), and read clear reversible write protection (rcrwp). . . . . . . . . . . . . . . . . . . . 20 7.10.3 read operations . . . . . . . . . . . . . . . . . . . . . . . 20 7.10.3.1 current address read . . . . . . . . . . . . . . . . . . . 20 7.10.3.2 selective read . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10.3.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . 21 7.11 hot plugging . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 register descriptions . . . . . . . . . . . . . . . . . . . 22 8.1 register overview. . . . . . . . . . . . . . . . . . . . . . 22 8.2 capability register (00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 23 8.3 con?guration register (01h, 16-bit read/write) . . . . . . . . . . . . . . . . . . 24 8.4 temperature format . . . . . . . . . . . . . . . . . . . . 28 8.5 temperature trip point registers . . . . . . . . . . 29 8.5.1 upper boundary alarm trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 29 8.5.2 lower boundary alarm trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 30 8.5.3 critical alarm trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 30 8.6 temperature register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 31 8.7 manufacturers id register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 32 8.8 device id register. . . . . . . . . . . . . . . . . . . . . . 32 8.9 smbus register. . . . . . . . . . . . . . . . . . . . . . . . 33 9 application design-in information . . . . . . . . . 34 9.1 SE97 in memory module application . . . . . . . 35 9.2 layout consideration . . . . . . . . . . . . . . . . . . . 35 9.3 thermal considerations . . . . . . . . . . . . . . . . . 35 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 36 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 44 13 soldering of smd packages . . . . . . . . . . . . . . 48 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 48 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 48 13.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 48 13.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 49 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 51 16 legal information . . . . . . . . . . . . . . . . . . . . . . 53 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 53 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53 17 contact information . . . . . . . . . . . . . . . . . . . . 53 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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